Simulation of the process of manufacturing of an integrated circuit has been proven to be invaluable for circuit designers and other alike as it helps to decrease very high costs of manufacturing and shortens the time to market dramatically. However, correct simulation of the process of manufacturing a physical design of an integrated circuit requires correct building of the manufacturing models. Nonetheless, accurate semiconductor manufacturing models usually involve enormous number of characteristics interacting with each other often in some non-linear manner. Therefore, correct semiconductor manufacturing modeling not only requires extremely high computing resources and oftentimes takes a long time to reach accurate results. As such, the construction of an accurate manufacturing model is usually very difficult. This problem is further aggravated by the fact that a modern integrated circuit often comprises many manufacturing process steps, and this increasingly complicated manufacturing process makes precise simulation of the results on wafers even more challenging.
Moreover, as the feature sizes in the modern IC layouts continue to shrink down to 65 nm or below, manufacturing process effects become harder to predict and control. A modern manufacturing process is extremely difficult to be modeled by a set of empirical rules and often requires computations based upon modeling the physical processes during the IC manufacturing. A modern manufacturing process includes many stages and many physical, chemical, mechanical, and electromagnetic effects to model. Modeling such a process requires very intensive numerical calculations.
As a result, a more practical and economical approach is to use empirical manufacturing process models containing various numbers of empirical manufacturing process parameters to simulate the manufacturing processes. These empirical manufacturing models require much less computing resources but are typically calibrated against experimental data so as to give reasonably close approximations of the manufacturing processes. Such empirical approximations contain parameters that may at best be roughly rather than accurately estimated and therefore must be calibrated to a specific process to achieve good modeling accuracy. Such a process of calibrating these empirical coefficients is called model calibration. The model calibration is now an inevitable and extremely important part of the modern manufacturing process simulation flow. Once the manufacturing process is fixed, a test layout comprising one or more geometrical patterns is designed and manufactured on a test wafer using this particular set of manufacturing processes. The resultant geometries on the wafer corresponding to the test patterns are then measured by using equipment such as a scanning electron microscope (SEM) with sufficient resolution. Thereafter, an empirical model of this particular process is prepared, and the parameters of the empirical model are adjusted so that the predictions by the empirical model best fit the experimental data collected from the experiment. Note that the adjustment of empirical model parameters may be performed manually, automatically by using special software applications, or semi-automatically.
Nanometrology is the science and practice of measurement that mostly concerns with dimensional parameters on components with at least one critical dimension which is smaller than 100 nm. Although still called microelectronics, the production of semiconductor devices with smallest feature widths well below 100 nm is the economically most important part of nanotechnology nowadays and presumably in the near future. In parallel with the shrinking dimensions of the components and structures produced in the semiconductor industry, the required measurement uncertainties for dimensional metrology in this important technology field are decreasing too. This contribution will provide an overview on developments in the field of nanometrology with a special focus on the demands from the semiconductor industry from the point of view of a metrology institute.
In many cases in nanometrology, the values of certain quantities such as geometrical dimensions of the sample's features cannot be measured directly, but must be extracted from a set of values obtained from direct measurement of other related quantities. For example, a measurement of the critical dimensions of an integrated circuit's feature consists of measuring the scattered electron beam intensity profile several times along a small section of the sample and numerical processing of the measured intensity profile to obtain the critical dimension value. Therefore, even using the same sample and same measurement device, different methods of numerical processing would lead to different values of the quantity. Also, the numerical processing algorithms involved into the extraction of the quantities of interest are very sensitive to the input data noise. Slight changes in feature wall angle, edge and surface roughness, or material properties can dramatically affect the precision and accuracy offset of the quantity being determined. Moreover, imaging characteristics for most types of precise measuring devices such as electron microscopes are not constant, which makes it even more difficult to perform accurate measurement.
Typically the process engineer will use in-house or “golden standards” to track the repeatability of a measurements. Unfortunately, variations in the features to be measured can cause the accuracy offset to change in ways that are unknown to the engineer. Furthermore, the offsets of multiple tools in a set, as well as differences in the numerical processing algorithms will not only change with respect to the reference but also relatively to each other. If these different measurement sets are used as an input for a process model calibration, the resulting calibrated models can easily be very much different, although related to the same reference sample.
Due to the increasingly complex manufacturing processes, the manufacturing models are usually calibrated against some experimental (or measured) data from a wafer with either some test patterns or other device patterns. Unless otherwise noted, the terms “experimental” and “measured” are used interchangeably throughout the entire Application to indicate or represent the information or data obtained from some test patterns or device patterns on a wafer. Once a manufacturing process is determined, a test layout or a test pattern is designed and reproduced on a wafer using the designated manufacturing process. The reproduced results on the wafer are then measured by using, for example, a scanning electron microscope (SEM) due to its high resolution to discern micro- or even nano-scale features on the wafer.
An empirical process model with one or more empirical process parameters may also be determined once the manufacturing process is determined. Note that the empirical process parameters may be adjusted such that the numerical predictions of the empirical process model better fit the data measured from the processed test patterns on a wafer.
Nonetheless, since the conventional modern manufacturing process modeling operates with the notion of a critical dimension of a layout feature, or the notion of a contour of a layout feature, it assumes that the printed layout features can be accurately approximated by step functions or near step functions, for the notions of the critical dimension or the notion of the contour to be accurately applicable. That is, modern manufacturing process modeling assumes that the sidewalls of the geometrical features on the wafer are vertical or almost vertical with clearly defined edges. For example, one-dimensional scan data have been used for the critical dimension (CD) extraction, while two-dimensional images are used for the feature contour extraction. This assumption has been proven, however, to be not the case for the modern low-contrast manufacturing processes at 65 nm and beyond, especially at the locations where the features become essentially two-dimensional, such as rounded line ends. With such low contrast manufacturing processes, the feature edges are no longer clearly defined but often appear to be “smeared” over some range defined by the specific feature topography.
FIGS. 1A-1C illustrate the impact of low-contrast images produced by a manufacturing process on the determination of locations of edges or contours of a feature of an integrated circuit. For example, as shown in FIGS. 1A-1C. The critical dimension or contour extraction becomes more problematic and less accurate as the edges become less clearly defined. FIG. 1A shows a feature with relatively clearly defined side walls. In this case, the width of the feature may be better determined by even the conventional edge or contour extraction algorithms.
FIG. 1B shows a feature with slant side walls. In this case, it is more difficult to determine the location of the “edges” of the feature, and as a result, the width of the feature depends heavily upon a predetermined threshold for the edge or contour extraction algorithm and thus may not be accurately determined. This problem is exacerbated as the semiconductor device geometries continue to shrink as it may be seen from FIG. 1C which illustrates a feature on a wafer with similar slant side walls but for a larger feature. In FIG. 1C, although the locations of the side walls are still more difficult to determine and may still heavily depend upon the predetermined threshold for the extraction algorithm, the impact of this imprecise determination of the contours of this particular feature in FIG. 1C is lessened as a result of the larger size of the feature.
Theoretically, a typical edge detection algorithm using a SEM analyzes the data collected from the SEM to determine the location of an edge. Where a test pattern is scanned by a SEM, the electron beam hitting a point on a flat surface produces lower signal than the signal hitting a point on a vertical or near vertical side. Thus, by analyzing the output signal, the edge detection algorithm may determine the location of an edge.
Conventional manufacturing model calibration methodologies usually use either critical dimension (CD) measurements or printed geometry contours for manufacturing process model calibration purposes. The problem with these conventional calibration methodologies is that neither the critical dimension measurements nor the printed geometry contours are produced directly by the measurement equipment such as a metrology tool. Rather, the critical dimensions and the printed geometry contours are typically extracted from the measurement data such as the SEM output data using various edge extraction algorithms which usually require extensive and thorough calibration before they may produce reasonable results. Often, two different edge extraction algorithms, even after extensive calibration, applied to the same geometrical pattern would produce different results. Therefore, the accuracy of such calibration methodologies is usually very sensitive to the choice of the edge extraction algorithm.
Another problem with such conventional calibration methodologies is that such edge extraction algorithms constitute inverse problems and thus are very sensitive to noises in the measurement data. These conventional model calibration methodologies' high sensitivity to noise in the measurement data is further aggravated as the ever increasingly shrinking feature sizes and the use of low-contrast manufacturing processes. As mentioned previously, one-dimensional scan data have been used for the critical dimension (CD) extraction, while two-dimensional images are used for the contour extraction. Both approaches inherently assume that the sidewalls can be well approximated by infinitely thin edges so that the notion of a feature edge can be clearly defined. Moreover, the extraction in both cases performed by some edge detection algorithms which contain one or more artificial parameters, a predefined threshold for example, which have to be calibrated using etalon measurements. In the modern low-contrast manufacturing processes, the measurement data are often noisy, and thus noise reduction and contrast enhancement methodologies are often required for the data collected from SEMs. More particularly, automatic contrast enhancement often fails to extract the edge data correctly, and thus such contrast enhancement methodologies often require manual enhancement.
As previously explained, edge detection algorithms analyze the collected SEM data to determine the locations of edges based upon the strength of the SEM output signals. Nonetheless, as the low-contrast manufacturing processes and ever increasingly shrinking feature sizes are more common in modern integrated circuit manufacturing, the side walls of features significantly differ from vertical and thus make the edge detection more difficult and more prone to noise due to the relatively lower ratio between SEM output signals from flat surfaces and those from edges.
Another approach is to use optical techniques such as optical scatterometry for tasks such as CD measurement rather than the electron microscope based metrology as described above. These optical techniques may be also be used for contour extraction, although typically with lower accuracy. For example, optical scatterometry instead of electron microscopy may be used for CD measurements. Scatterometry is a non-destructive optical technique that records and analyzes interference of light reflected from a scattering surface. By measuring and analyzing the light diffracted from a sample, the dimensions of the sample itself can be measured. Scatterometry exploits the sensitivity of diffraction from a sample to changes in the topography of the sample.
In optical scatterometry, information of the printed features of an integrated circuit may be obtained by illuminating the printed features of the integrated circuit with an optical beam and measuring the distribution of the light diffracted on these features. These optical methods such as the scatterometry described immediately above still suffer, however, similar problems as the metrology techniques employing electron microscopes or similar devices. For example, these metrology techniques require algorithms to solve complicated inverse problems. Moreover, the low-contrast images as a result of the modern low-contrast manufacturing processes pose the same problems with defining the contours, edges, or critical dimensions. Furthermore, as scatterometry exploits the sensitivity of diffraction from the sample, this method is also sensitive to noise in the information collected.